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arago

ashby arago · public job-board evidence · tracked since 2026-09-01

HQ (inferred): FR (inferred) · Careers page

Company-level public facts only — no personal contact data.

All roles in explorer

Open roles

0.0%

Salary disclosure rate

n=0 stated ranges

—

Median salary (USD)

sample too small (n=0 < 5)

Countries

Hiring signal

+0.0% open roles (30d)

2 roles opened and 2 closed in the last 30 days of live observation.

Open roles by job family

Median stated pay by level

stated only

Change events

2026-10-01 retitled Senior Verification Engineer · was “Senior Digital Verification Engineer”
2026-09-28 retitled Senior Verification Engineer · was “Senior Mixed-Signal Verification Engineer”
2026-09-28 retitled Digital IC Design Engineer · was “Mixed-Signal IC Design Engineer”
2026-09-28 retitled Senior Analog IC Design Engineer · was “Senior Analog Design Engineer”
2026-09-18 closed AI/ML Scientist — Quantization & Numerical Robustness · open 16.8 days
2026-09-16 closed Senior Hardware Design Engineer · open 1.3 days
2026-09-09 closed Full-Stack Engineer, Office of the CEO · open 8.0 days
2026-09-08 closed Software Engineer — Drivers & Virtualization · open 6.8 days
2026-09-07 closed PCB Design Engineer · open 5.8 days
2026-09-02 retitled Senior Analog IC Design Engineer · was “Senior RF/Analog Design Engineer”

Derived from consecutive dated observations of this board — salary revisions, retitles, closings. Timestamps are observation times, not employer statements.

Current evidence

Recent open roles

Every row links back to its public source.

Role & company	Location	Stated pay	Evidence
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